搜索资源列表
8.10
- 强烈推荐下载,verilog状态机实例.可以在modelsim下运行. -strongly recommend downloading Verilog state machine example. In modelsim running.
trafficLight-verilog
- 交通灯状态机的实现,用verilog HDL编程,Xilinx ISE 6仿真,在实际电路中得到验证.-traffic lights to achieve the state machine, with verilog HDL programming, Xilinx ISE 6 simulation, the actual circuit have been tested.
3-1
- 自动卖报机,5分一份,有1,2,5分类型的硬币。verilog状态机
verilog
- 一个简单状态机的.v文件,含testbench
FPGA控制AD程序,ADC,DAC转换接口
- FPGA控制AD程序,ADC,DAC转换接口.rar 有限状态机控制AD采样.rar,FPGA control AD procedure
Verilog
- Verilog三段式状态机描述,本章内容详细的介绍了Verilog三段式状态机描述,进一步加深对Verilog的认识-Verilog descr iption of three-stage state machine, this chapter introduces Verilog detailed descr iption of three-stage state machine, and further deepen the understanding of Verilog 朗读 显
SDH
- SDH开销的接收处理,要求: 1, A1和A2字节为帧头指示字节,A1为“11110110”,A2为“00101000”,连续3个A1字节后跟连续3个A2字节表示SDH一帧的开始。要求自行设计状态机,从连续传输的SDH字节流中找出帧头。 2, E2字节为勤务话通道开销,用于公务联络语音通道,其比特串行速率为64KHz(8*8K=64)。要求从SDH字节流中,提取E2字节,并按照64K速率分别串行输出E2码流及时钟,其中64K时钟要求基本均匀。(输出端口包括串行数据和64K串行时钟)
max197
- verilog编写的状态机控制A/D芯片MAX197正常工作-use verilog write the state machine which is used to meke the A/D chip working!
lpc
- LPC总线从设备的verilog设计,包含状态机和中断功能。-verilog code for LPC device
Chapter6-9
- 第六章到第九章的代码 本书通过100多个模块实例,详细地讲解了Verilog HDL程序设计语言,全书共分13章,内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等,实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例
4bit_buma_adder
- Verilog作业 :自己写的源码输入,补码输出的,由状态机控制的四位加法器,为保证时序,加法器模块为超前近位加法器,包含测试台,通过 Modelsim 、Synplify仿真。-Verilog operation: the source code to write their own input, complementary code output by the state machine to control the four adder, in order to ensure timing
vtbird_21
- 雷鸟车尾灯状态机,vhdl实现,对学习VHDL的同学有帮助。-Thunderbird taillights state machine, vhdl realize, the study has helped students VHDL.
IIC_AD75
- I2C温度传感器ADT75的控制源码 使用verilog 状态机实现 易入门-I2C for ADT75 temperature sensor
IOcontrol
- 输入输出控制的状态机,verilog HDL源码-Input and output control state machine, verilog HDL source
JIJIAQI
- Quartus II工程压缩文件,是一个典型的基于FPGA的计价器工程项目,有有限状态机、50MHz分频、计数、译码、动态扫描等模块。-Quartus II project files, is a typical FPGA-based project of the meter, there are finite state machine, 50MHz frequency, counting, decoding, dynamic scanning module.
telephone
- 实现长途电话,市话的计时,还有免费电话 在verilog中用状态机实现-The achievement of long-distance calls, the city of the time, then, there are toll-free number in verilog state machine used to achieve
123
- 基于quartus的,状态机实现流水灯,verilog HDL语言编写-Quartus-based, the state machine to achieve water lights, verilog HDL language
AD0809
- verilog实现的“状态机实现AD0809数模转换”。-verilog to achieve a " state machine to achieve AD0809 digital to analog conversion."
miaobiao
- 用VERILOG实现秒表的开发设计,(1)熟悉按键扫描、按键防抖和数码管驱动接口电路原理;(2)掌握按键扫描、按键防抖和数码管驱动接口电路设计开发;(3)掌握状态机实际应用设计。-To achieve the development of a stopwatch with VERILOG Design, (1) be familiar with key scanning, image stabilization and digital control key driver interface c
Chapter11-13
- 第十一章到第十三章的代码 本书通过100多个模块实例,详细地讲解了Verilog HDL程序设计语言,全书共分13章,内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等,实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个